View Z9952AA_4152482.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer Product Features
* * * * * * * * * * * * 180MHz Clock Support 150ps Maximum Output to Output Skew TM Supports PowerPC , Intel and RISC Processors 11 Clock Outputs: Frequency Configurable Outputs Drive up to 22 Clock Lines LVCMOS/LVTTL Compatible Inputs Output Tri-state Control Spread Spectrum Compatible 3.3V Power Supply Pin Compatible with MPC952 Industrial Temp. Range: -40C to +85C 32-Pin TQFP Package
Frequency Table
VCO_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL (A:C) 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 QA(0:4) VCO/4 VCO/4 VCO/4 VCO/4 VCO/6 VCO/6 VCO/6 VCO/6 VCO/8 VCO/8 VCO/8 VCO/8 VCO/12 VCO/12 VCO/12 VCO/12
Table 1
QB(0:3) VCO/4 VCO/4 VCO/2 VCO/2 VCO/4 VCO/4 VCO/2 VCO/2 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4
QC (0,1) VCO/2 VCO/4 VCO/2 VCO/4 VCO/2 VCO/4 VCO/2 VCO/4 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8
Block Diagram
PLL_EN# REFCLK FB_IN
LPF
Phase Detector
VCO 200-480M
/2
/4, /6
QA0 QA1 QA2 QA3 QA4
Pin Configuration
VCO_SEL SELA
/4, /2
VDDC
QB0 QB1
32
31
30
29
28
27
26
SELB
QB2 QB3
/2, /4
QC0 QC1
9
10
11
12
13
14
15
PLL_EN#
QA0
VSS
QA1
VDDA
QA2
Figure 1
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07085 Rev. *B
VDDC
VDD
16
SELC MR/OE#
VCO_SEL SELC SELB SELA MR/OE# REFCLK VSS FB_IN
1 2 3 4 5 6 7 8
25 24 23 22 21 20 19 18 17
VDDC
QC1
QC0
QB3
QB2
VSS
VSS
Z9952
VSS QB1 QB0 VDDC VDDC QA4 QA3 VSS
12/22/2002 Page 1 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer Pin Description
PIN 6 12, 14, 15, 18, 19 22, 23, 26, 27 30, 31 8 1 NAME REFCLK QA(0:4) QB(0:3) QC(0,1) FB_IN VCO_SEL PWR VDDC VDDC VDDC I/O I O O O I I, PD Description External Test Clock Input. Clock Output. See Frequency Table. Clock Output. See Frequency Table. Clock Outputs. See Frequency Table.
Feedback Clock Input. Connect to an output for normal operation.
5
MR/OE#
I, PD
9 2, 3, 4
PLL_EN# SEL(C:A)
I I, PD
16, 20, 21, 25, 32 10 11 7, 13, 17, 24, 28, 29
VDDC VDDA VDD VSS
VCO Divider Select Input. When set high, the VCO output is divided by 2. When set low, the divider is bypassed. See Table 1 Master Reset/Output Enable Input. When asserted high, resets all of the internal flip-flops and also disables all of the outputs. When pulled low, releases the internal flip-flops from reset and enables all of the outputs. PLL Enable Input. When asserted low, PLL is enabled. And when set high, PLL is bypassed. Frequency Select Inputs. See Frequency Table. If SEL_ = 0, then QA, QB divider = /4, QC divider = /2 If SEL_ = 1, then QA divider = /6, QB divider = /2, QC divider = /4 3.3V Power Supply for Output Clock Buffers. 3.3V Power Supply for PLL 3.3V Power Supply for Core Logic Common Ground
PD = Internal Pull-Down
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002 Page 2 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS - 0.3V Maximum Input Voltage Relative to VDD: VDD + 0.3V Storage Temperature: Operating Temperature: Maximum ESD protection Maximum Power Supply: Maximum Input Current: -65C to + 150C -40C to +85C 2KV 5.5V 20mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)DC Parameters
Characteristic Input Low Voltage Input High Voltage Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Output Low Voltage Output High Voltage Quiescent Supply Current PLL Supply Current Input Capacitance Symbol VIL VIH IIL IIH VOL VOH IDDC IDD Cin Min VSS 2.0 Typ Max 0.8 VDD 10 120 0.5 20 20 4 Units V V A A V V 15 15 mA mA pF Conditions
Note 2 IOL = 20mA, Note 3 IOH = -20mA, Note 3 All VDDC, VDDA, and VDD VDDA only
2.4 -
VDDA = VDD = VDDC = 3.3V 5%, TA = -40C to +85C
Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Note 2: Inputs have internal pull-down resistors that affect input current. Note 3: Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002 Page 3 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer AC Parameters1
SYMBOL
Freq Fvco Tlock Tr / Tf Fout
PARAMETER
Reference Input Frequency PLL VCO Lock Range Maximum PLL lock Time Output Clocks Rise / Fall Time Maximum Output Frequency
4,5
MIN
Note 2 200 0.10 -
TYP
MAX
Note 2 480 10 1.0 180 120 80
UNITS
MHz MHz ms ns MHz
CONDITIONS
0.8V to 2.0V QB, QC = (/2) QA, QB, QC = (/4) QA = (/6)
FoutDC tpZL, tpZH tpLZ, tpHZ TCCJ Tpd TSKEW0
Output Duty Cycle
4,5
TCYCLE/2 - 750 2 2
5
TCYCLE/2 + 750 10 8 +/- 100 200 150 250
ps ns ns ps ps ps Same frequencies Different frequencies
Output enable time (all outputs) Output disable time (all outputs) Cycle to Cycle Jitter (peak to peak) REFCLK to FB_IN Delay
3,,4,5 4,5
-200 -
Any Output to Any Output Skew
VDDA = VDD = VDDC = 3.3V +/- 5%, TA = -40C to +85C Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. Note 2: Maximum and minimum input reference is limited by the VCO lock range. Note 3: The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the minimum limits with an increase/decrease of the input reference clock period. Note 4: Driving series or parallel terminator 50 (or 50 to VDD/2). Note 5: Outputs loaded with 30pF each
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002 Page 4 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer Description
The Z9952 has an integrated PLL that provides low skew and low jitter clock outputs for high performance microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to 180MHz. The Z9952 features three banks of individually configurable outputs: Bank A five outputs, Bank B four outputs, and Bank C two outputs. When MR/OE# input is set high, all the outputs are tri-stated. The Z9952 outputs are LVCMOS compatible and can drive two series terminated 50 transmission lines. With this capability the Z9952 has an effective fanout of 1:22. Low output-to-output skews make the Z9952 ideal for clock distribution in nested clock trees in the most demanding of synchronous systems. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by SEL(A:C) select inputs, see Table 2. The VCO_SEL input allows for the choice of two VCO ranges to optimize PLL stability and jitter performance, see Table 1. The VCO frequency is then divided down to provide the required output frequencies. The use of even dividers ensures that the output duty cycle remains at 50%.
SELA 0 1
QA /4 /6
SELB 0 1
QB /4 /2
SELC 0 1
QC /2 /4
Table 2
Zero Delay Buffer
When used as a zero delay buffer the Z9952 will likely be in a nested clock tree application. Any of the eleven outputs can be used as the feedback to the PLL. By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the Z9952 is a function of the configuration used.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002 Page 5 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer Package Drawing and Dimensions
32 Pin TQFP Outline Dimensions
INCHES SYMBOL A D A1 A2 D D1 D1 12 A1 A L e b b e L 0.018 0.002 0.037 0.012 0.354 0.276 0.031 BSC 0.030 0.45 0.006 0.041 0.018 0.05 0.95 0.30 9.00 7.00 0.80 BSC 0.75 0.15 1.05 0.45 MIN NOM MAX 0.047 MIN MILLIMETERS NOM MAX 1.20
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002 Page 6 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer Ordering Information
Part Number Package Type Production Flow Z9952AA 32 PIN TQFP Industrial, -40C to +85C Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress Z9952AA Date Code, Lot #
Z9952AA
Package A = TQFP Revision IMI Device Number
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002 Page 7 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002 Page 8 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Document Title: Z9952 3.3V, 180 MHz Multi-Output Zero Delay Buffer Document Number: 38-07085
Rev. ** *A *B
ECN No. 107121 108064 122770
Issue Date 06/05/01 07/03/01 12/22/02
Orig. of Change IKA NDP RBI
Description of Change Convert from IMI to Cypress Changed Commercial to Industrial Add power up requirements to maximum ratings information
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002 Page 9 of 9

▲Up To Search▲

Price & Availability of Z9952AA

	To Download Z9952AA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .